Cases

You are welcome to submit a challenge at a.sadovykh@innopolis.ru

MTS - Employee self-improvement and time-tracking facilitation

MTS is the largest mobile network operator in Russia, operating on GSM, UMTS and LTE standards. Apart from cellular network, the company also offers local telephone service, broadband, mobile television, cable television, satellite television and digital television.

Context: MTS would like to help its employees to be more productive. Personal tasks planning, estimations and tracking is a proven way to self-improvement in terms of performance and quality. The challenge is that manually collecting plans, estimates and time reports are a very tedious and effort consuming activities that may divert employees from a good practice. Employees, senior and junior developers are happy to try and look at the analysis however they need a very simple tool that would help them to track time and sync with tasks in Jira in a automated way as much as possible.

Tasks: Analyse available tools, evaluate applicability in the customer's context, give recommendations on effective combination of tools.

Constraints: One task per moment, Jira as the task tracker,

The analysis problem may be further refined during the interviews.

Electronic Design Automation (EDA)

Yuri Panchul is an electronic chip designer (MIPS, Juniper and other companies); a founder of an EDA startup C Level Design acquired by Synopsys, an editor of a book published by HSE MIEM and an author of an online course developed by RUSNANO.

Context: When a chip architect gives a hardware block designer the architectural specification for a new block, he also gives the designer a set of requirements. These requirements include:

  1. The performance or bandwidth: a number of instructions, transactions, network packets or graphical primitives processed by the block in a number of clock cycles.

  2. The timing budget: the number of picoseconds available for the combinational logic to stabilize within one clock period. In order words, the required clock frequency.

  3. The total area budget, which includes the area for the embedded SRAMs and the ASIC standard cells.

In addition, the designer gets guidance on power optimization. One of the key metrics related to both area and power is the count of D-flip-flops (DFFs), the main state elements in digital design. DFFs are used to build hardware pipelines, state machines, FIFO queues and CPU scoreboards. The designer:

  1. Receives the DFF budget from the chip architect;

  2. Estimates the number of DFFs required for each sub-block early in the design cycle; and

  3. Tracks this number every week till the chip tapeout.

A digital design is almost always done using a hardware description language: Verilog, SystemVerilog or VHDL. The technology that converts a Verilog code into a graph of logic elements is called logic synthesis. The synthesis technology is complicated and not suitable for a hackathon. However it is possible to approximately count the number of DFFs even without full synthesis, just by finding so-called non-blocking assignments in Verilog code and adding the sizes of the variables on the left-hand sides of non-blocking assignments.

Task: Write a program that estimates the number of D-flip-flops in an electronic circuit by a quick analysis of its Verilog source code.

Instruments: this problem has multiple levels of difficulty, depending on how much Verilog syntax we are willing to support:

  1. If we restrict the input code to single-bit variables within a single module, we can write just a few Linux commands that do the job. We can grep for '<=' non-blocking assignment characters, then collect the unique identifiers on the left-hand sides of non-blocking assignments and report their number. An experienced Linux user can write a simple "grep|sed|sort|wc" pipeline for it in a few minutes.

  2. A more complicated case, with parsing bit vectors and unpacked arrays, would take longer, up to several hours. You can use regular expressions in Python or Lex & Yacc - style parsers in C or Java.

  3. If we are going to support counting DFFs in the Verilog module hierarchy, we need to parse module instantiations and build the instance tree. This adds hours of programming but can still be done during a short hackathon.

  4. If we extend the task to support Verilog preprocessor, parameterized modules, "generate" constructs, "struct" types and the assignments inside Verilog "tasks", we probably need a "real" Verilog parser. There are some open-source parsers of Verilog, including Yosys, Icarus Verilog and Verilator. Your hackathon team can study and utilize them if you wish to go this way.

Whatever you decide to do you are likely to get a good experience in scripting, compilers and digital design.

For more details see the description of the project in an article on the Habr website (in Russian) https://habr.com/ru/post/702186/